IEEE - Institute of Electrical and Electronics Engineers, Inc. - Novel test structures for the characterization of latch-up tolerance in a bipolar and MOSFET merged device

Author(s): Momose, H. ; Maeda, T. ; Inoue, K. ; Urakawa, Y. ; Maeguchi, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Kyoto, Japan
Conference Date: 18 March 1990
Page(s): 225 - 230
ISBN (Paper): 0-87942-588-1
DOI: 10.1109/ICMTS.1990.161747
Regular:

A novel test structure was used to evaluate a latchup phenomenon in a bipolar and MOSFET merged device for the BiNMOS gate. Its characteristics were analyzed by varying the test pattern. In the... View More

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