IEEE - Institute of Electrical and Electronics Engineers, Inc. - Parasitic BJT design consideration in SOI MOSFETs

Author(s): Her, T.-D. ; Liu, P.S. ; Li, G.P. ; Chi, C. ; Brandewie, J. ; White, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Key West, FL, USA, USA
Conference Date: 2 October 1990
Page(s): 34 - 35
ISBN (Paper): 0-87942-573-3
DOI: 10.1109/SOSSOI.1990.145696
Regular:

In an n-channel silicon-on-insulator (SOI) MOSFET the accumulation of holes in the floating substrate can lead to the rise of the substrate potential and thus turn on the parastic... View More

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