IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 65nm 0.08-to-680MHz Synthesizable MDLL with Nested-Delay Cell and Background Static Phase Offset Calibration

Author(s): Dong-Jin Chang ; Min-Jae Seo ; Hyeok-Ki Hong ; Seung-Tak Ryu
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Paper): 1549-7747
ISSN (Online): 1558-3791
DOI: 10.1109/TCSII.2017.2689029
Regular:

This paper presents a wide frequency-range synthesizable multiplying delay-locked-loop (MDLL) with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes... View More

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