IEEE - Institute of Electrical and Electronics Engineers, Inc. - 2 x VDD 40-nm CMOS Output Buffer with Slew Rate Self-adjustment Using Leakage Compensation

Author(s): Chua-Chin Wang ; Zong-You Hou ; Kai-Wei Ruan
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Paper): 1549-7747
ISSN (Online): 1558-3791
DOI: 10.1109/TCSII.2016.2599538
Regular:

A 2VDD output buffer for 40 nm CMOS technology nodes is proposed in this investigation featured with slew rate (SR) auto-adjusted by PVTL (process, voltage, temperature, leakage) detection, and... View More

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