IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes.
|Author(s):||Tiansong Cui ; Ji Li ; Yanzhi wang ; Shahin Nazarian ; Massoud Pedram|
|Sponsor(s):||IEEE Computer Society|
|Publisher:||IEEE - Institute of Electrical and Electronics Engineers, Inc.|
With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In... View More
With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- and super-threshold (VT ) operation regimes. The impacts of Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using one of the most advanced technology nodes - a 7nm FinFET technology. The paper starts with design and optimization of 7nm FinFET devices using the Synopsys TCAD suite. Next, equivalent circuit models of FinFET devices are built and Verilog-A format parameters are extracted. Based on the circuit models, multiple standard cell libraries using different leakage reduction techniques, such as GLB and Dual-VT , are built in multiple voltage operating regimes. It is demonstrated that compared to Dual-VT , GLB is a more suitable technique for the advanced 7nm FinFET technology, due to its capability of delivering a fine-grained tradeoff between the leakage power and circuit speed, not to mention the lower manufacturing cost. The circuit synthesis results of a variety of ISCAS benchmark circuits using the presented GLB 7nm FinFET cell libraries show up to 70% leakage improvement with zero degradation in circuit speed in the near- and super-VT regimes, respectively, compared to the standard 7nm FinFET cell library. This paper also presents a detailed analysis of the benefits and constraints of the transistor-level GLB technique, in which each transistor can individually modify delays of different timing arcs. Results show that up to 10% of leakage power reduction can be further achieved by applying transistor-level GLB technique in near-VT regime at the expense of increased cell library size.View Less