IEEE - Institute of Electrical and Electronics Engineers, Inc. - Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

Author(s): Taizhi Liu ; Chang-Chih Chen ; Linda Milor
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Online): 2168-6750
DOI: 10.1109/TETC.2016.2588724
Regular:

A framework is proposed to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including... View More

Advertisement