IEEE - Institute of Electrical and Electronics Engineers, Inc. - Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures

Author(s): Travis Boraten ; Avinash Kodi
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/TCAD.2017.2664066
Regular:

As aggressive scaling continues to push Multi- Processor System-on-Chips (MPSoCs) to new limits, complex hardware structures combined with stringent area and power constraints will continue to... View More

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