IEEE - Institute of Electrical and Electronics Engineers, Inc. - SDPR: Improving Latency and Bandwidth in On-Chip Interconnect through Simultaneous Dual-Path Routing

Author(s): Yoon Seok Yang ; Hrishikesh Deshpande ; Gwan Choi ; Paul V. Gratz
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/TCAD.2016.2570428
Regular:

Networks-on-chips (NoCs) are gaining in popularity as replacement for shared medium interconnects in chipmultiprocessors (CMPs) and multiprocessor systems-on-chips (MPSoCs), and their performance... View More

Advertisement