IEEE - Institute of Electrical and Electronics Engineers, Inc. - Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

Author(s): Nupur Navlakha ; Jyi-Tsong Lin ; Abhinav Kranti
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2017
Volume: 64
Page(s): 1,561 - 1,567
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2017.2662703
Regular:

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing... View More

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