IEEE - Institute of Electrical and Electronics Engineers, Inc. - Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

Author(s): Zhiwei Li ; Pai-Yu Chen ; Haijun Liu ; Qingjiang Li ; Hui Xu ; Shimeng Yu
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2017
Volume: 64
Page(s): 1,568 - 1,574
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2017.2665642
Regular:

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the... View More

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