IEEE - Institute of Electrical and Electronics Engineers, Inc. - Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its Variations With Geometrical Parameters

Author(s): Savitesh Madhulika Sharma ; Sudeb Dasgupta ; M. V. Kartikeyan
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 2017
Volume: 64
Page(s): 384 - 391
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2016.2641039
Regular:

We propose a new analytical model based on successive conformal mapping to compute the bias dependent inner fringe capacitance in nonplanar multigate MOSFET structure with doping modulated... View More

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