IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Analytical Model of Drain Current in a Nanoscale Circular Gate TFET

Author(s): Rupam Goswami ; Brinda Bhowmick
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2017
Volume: 64
Page(s): 45 - 51
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2016.2631532
Regular:

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular... View More

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