IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

Author(s): Behnam Jafari Touchaei ; Negin Manavizadeh
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2017
Volume: 64
Page(s): 306 - 311
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2016.2626342
Regular:

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of... View More

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