IEEE - Institute of Electrical and Electronics Engineers, Inc. - Comparison of SOI Versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node

Author(s): Xi Zhang ; Daniel Connelly ; Hideki Takeuchi ; Marek Hytha ; Robert J. Mears ; Tsu-Jae King Liu
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2017
Volume: 64
Page(s): 329 - 332
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/TED.2016.2626397
Regular:

The electrostatic benefit of using a silicon-on-insulator (SOI) wafer substrate versus a bulk-silicon wafer substrate with optimized supersteep retrograde (SSR) doping for a low-power... View More

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