IEEE - Institute of Electrical and Electronics Engineers, Inc. - Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

Author(s): S. Maheshwaram ; S. K. Manhas ; G. Kaushal ; B. Anand ; N. Singh
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2012
Volume: 33
Page Count: 3
Page(s): 934 - 936
ISSN (Paper): 0741-3106
ISSN (Online): 1558-0563
DOI: 10.1109/LED.2012.2197592
Regular:

In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source-drain extension... View More

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