IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Author(s): E. Temporiti ; C. Weltin-Wu ; D. Baldi ; R. Tonietto ; F. Svelto
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2009
Volume: 44
Page Count: 11
Page(s): 824 - 834
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.2008.2012363
Regular:

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF... View More

Advertisement