IEEE - Institute of Electrical and Electronics Engineers, Inc. - A framework for the characterization and verification of embedded phase-locked loops

Author(s): T. Egan ; S. Mourad
Sponsor(s): IEEE Instrumentation and Measurement Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2002
Volume: 51
Page Count: 6
Page(s): 1,234 - 1,239
ISSN (Paper): 0018-9456
ISSN (Online): 1557-9662
DOI: 10.1109/TIM.2002.807983
Regular:

With the increasing use of phase-locked loops (PLLs) embedded in FPGAs, ASICs, and system-on-chip (SOC), there is a growing need for methods to verify their operation. This paper describes a... View More

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