IEEE - Institute of Electrical and Electronics Engineers, Inc. - Diminished-one modulo 2/sup n/+1 adder design

Author(s): H.T. Vergos ; C. Efstathiou ; D. Nikolos
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Distributed Process
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2002
Volume: 51
Page Count: 11
Page(s): 1,389 - 1,399
ISSN (Paper): 0018-9340
DOI: 10.1109/TC.2002.1146705
Regular:

This paper presents two new design methodologies for modulo 2/sup n/+1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to... View More

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