IEEE - Institute of Electrical and Electronics Engineers, Inc. - Buffer block planning for interconnect planning and prediction

Author(s): J. Cong ; Tianming Kong ; Z.D. Pan
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2001
Volume: 9
Page Count: 9
Page(s): 929 - 937
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.974906
Regular:

This paper studies buffer block planning (BBP) for interconnect planning and prediction in deep submicron designs. We first introduce the concept of a feasible region for buffer insertion, and... View More

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