IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delay fault testing of IP-based designs via symbolic path modeling

Author(s): Hyungwon Kim ; J.P. Hayes
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2001
Volume: 9
Page Count: 18
Page(s): 661 - 678
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.953500
Regular:

Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SoC) designs. The implementation details of IP cores are often unknown or... View More

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