IEEE - Institute of Electrical and Electronics Engineers, Inc. - On gate level power optimization using dual-supply voltages

Author(s): Chunhong Chen ; A. Srivastava ; M. Sarrafzadeh
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2001
Volume: 9
Page Count: 14
Page(s): 616 - 629
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.953496
Regular:

In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze... View More

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