IEEE - Institute of Electrical and Electronics Engineers, Inc. - On optimal tapering of FET chains in high-speed CMOS circuits

Author(s): Li Ding ; P. Mazumder
Sponsor(s): IEEE Circuits & Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2001
Volume: 48
Page Count: 11
Page(s): 1,099 - 1,109
ISSN (Paper): 1057-7130
DOI: 10.1109/82.988935
Regular:

Transistor tapering is a technique applied to optimize the geometries of CMOS transistors in high-performance circuit design with a view to minimizing the delay of a FET network. Currently, in a... View More

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