IEEE - Institute of Electrical and Electronics Engineers, Inc. - Some space considerations of VLSI systolic array mappings

Author(s): J.H. Weston ; C.N. Zhang ; Hua Li
Sponsor(s): IEEE Circuits & Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2001
Volume: 48
Page Count: 6
Page(s): 419 - 424
ISSN (Paper): 1057-7130
DOI: 10.1109/82.933810
Regular:

In this brief, the space-time mapping of the dependency matrix of an algorithm is used to study spatial properties of a systolic array implementation of a three-nested loop structure. Elementary... View More

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