IEEE - Institute of Electrical and Electronics Engineers, Inc. - Residual thermomechanical stresses in thinned-chip assemblies

Author(s): S. Leseduarte ; S. Marco ; E. Beyne ; R. Van Hoof ; A. Marty ; S. Pinel ; O. Vendier ; A. Coello-Vera
Sponsor(s): IEEE Components, Packaging, and Manufacturing Technology Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2000
Volume: 23
Page Count: 7
Page(s): 673 - 679
ISSN (Paper): 1521-3331
ISSN (Online): 1557-9972
DOI: 10.1109/6144.888852
Regular:

A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this... View More

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