IEEE - Institute of Electrical and Electronics Engineers, Inc. - Solder bump reliability-issues on bump layout

Author(s): T. Alander ; P. Heino ; E. Ristolainen
Sponsor(s): IEEE Components, Packaging, and Manufacturing Technology Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2000
Volume: 23
Page Count: 6
Page(s): 715 - 720
ISSN (Paper): 1521-3323
ISSN (Online): 1557-9980
DOI: 10.1109/6040.883763
Regular:

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the... View More

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