IEEE - Institute of Electrical and Electronics Engineers, Inc. - Wafer-level chip scale packaging: benefits for integrated passive devices

Author(s): H.M. Clearfield ; J.L. Young ; S.D. Wijeyesekera ; E.A. Logan
Sponsor(s): IEEE Components, Packaging, and Manufacturing Technology Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2000
Volume: 23
Page Count: 5
Page(s): 247 - 251
ISSN (Paper): 1521-3323
ISSN (Online): 1557-9980
DOI: 10.1109/6040.846642
Regular:

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with "fine... View More

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