IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets

Author(s): S. Deleonibus ; C. Caillat ; G. Guegan ; M. Heitzmann ; M.E. Nier ; S. Tedesco ; B. Dal'zotto ; F. Martin ; P. Mur ; A.M. Papon ; G. Lecarval ; S. Biswas ; D. Souil
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2000
Volume: 21
Page Count: 3
Page(s): 173 - 175
ISSN (Paper): 0741-3106
ISSN (Online): 1558-0563
DOI: 10.1109/55.830972
Regular:

We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N/sup -/... View More

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