IEEE - Institute of Electrical and Electronics Engineers, Inc. - A design for testability scheme to reduce test application time in full scan

Author(s): Pradhan, D.K. ; Saxena, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1992
Conference Location: Atlantic City, NJ, USA, USA
Conference Date: 7 April 1992
Page(s): 55 - 60
ISBN (Paper): 0-7803-0623-6
DOI: 10.1109/VTEST.1992.232724
Regular:

Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in... View More

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