IEEE - Institute of Electrical and Electronics Engineers, Inc. - A partitioning approach to design fault-tolerant arithmetic arrays

Author(s): Thou-Ho Chen ; Liang-Gee Chen ; Yeu-Shen Jehng
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1992
Conference Location: Scottsdale, AZ, USA, USA
Conference Date: 1 April 1992
Page(s): 432 - 439
ISBN (Paper): 0-7803-0605-8
DOI: 10.1109/PCCC.1992.200588
Regular:

An alternative fault-tolerant design in VLSI-based arithmetic arrays using the partitioning technique is presented. The basic concept is that the arithmetic array can be divided into m parts and... View More

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