IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hardware based error and flow control in the Axon gigabit host-network interface

Author(s): Sterbenz, J.P.G. ; Kantawala, A. ; Buddhikot, M.M. ; Parulkar, G.M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1992
Conference Location: Florence, Italy
Conference Date: 1 May 1992
ISBN (Paper): 0-7803-0602-3
DOI: 10.1109/INFCOM.1992.263586
Regular:

The primary goal of the Axon architecture is to support a high-performance data path delivering high network bandwidth directly to applications. The Axon network interface is described from the... View More

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