IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and performance of phase-lock circuits capable of near-optimum performance over a wide range of input signal and noise levels

Author(s): R. Jaffe ; E. Rechtin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 1955
Volume: 1
Page(s): 66 - 76
ISSN (Paper): 0096-1000
ISSN (Online): 2168-2712
DOI: 10.1109/TIT.1955.1055125
Regular:

Phase locked loops (PLLs) provide an efficient method for detection and tracking of narrow-band signals in the presence of wide-band noise. This paper explains how minimum-rms-error loops may be... View More

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