IEEE - Institute of Electrical and Electronics Engineers, Inc. - G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing

Author(s): Silberman, G.M. ; Spillinger, I.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1988
Conference Location: Washington, DC, USA, USA
Conference Date: 12 September 1988
Page(s): 764 - 772
ISBN (Paper): 0-8186-0870-6
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1988.207863
Regular:

A formal approach to the analysis of combinatorial gate-level designs is presented which produces information conducive to the acceleration of test generation algorithms. This analysis yields, as... View More

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