IEEE - Institute of Electrical and Electronics Engineers, Inc. - Double stacked capacitor with self-aligned poly source/drain transistor (DSP) cell for megabit DRAM

Author(s): Tsukamoto, K. ; Shimizu, M. ; Inuishi, M. ; Matsuda, Y. ; Oda, H. ; Morita, H. ; Nakajima, M. ; Kobayashi, K. ; Mashiko, Y. ; Akasaka, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1987
Conference Location: Washington, DC, USA, USA
Conference Date: 6 December 1987
Page(s): 328 - 331
DOI: 10.1109/IEDM.1987.191423
Regular:

A novel DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench.... View More

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