IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Pipelined 330 MHz Multiplier

11th European Solid State Circuits Conference

Author(s): Schmitt-Landsiedel, D. ; Noll, T.G. ; Klar, H. ; Enders, G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 1985
Conference Location: Toulouse, France, France
Conference Date: 16 September 1985
Page(s): 9 - 12
Regular:

An 8 +ù 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc... View More

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