IEEE - Institute of Electrical and Electronics Engineers, Inc. - Comparison of latch-up in p- and n-well CMOS circuits

Author(s): Takacs, D. ; Harter, J. ; Jacobs, E.P. ; Werner, C. ; Schwabe, U. ; Winnerl, J. ; Lange, E.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1983
Conference Location: Washington, DC, USA, USA
Conference Date: 5 December 1983
Page(s): 159 - 163
DOI: 10.1109/IEDM.1983.190466
Regular:

The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical... View More

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