IEEE - Institute of Electrical and Electronics Engineers, Inc. - Realization of digital filter algorithms by use of a high speed parallel processing architecture

IEEE International Conference on Acoustics, Speech, and Signal Processing

Author(s): Steinmetz, R. ; Gemballa, R. ; Lenzer, J. ; Roth, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1983
Conference Location: Boston, Massachusetts, USA, USA
Conference Date: 14 April 1983
Volume: 8
Page(s): 1,188 - 1,191
DOI: 10.1109/ICASSP.1983.1171973
Regular:

This paper presents a system, which generates code for a high speed parallel computer architecture taking as input the tolerance schemes of digital filters. The multi-processor system consists of... View More

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