IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test Generation for MOS Circuits Using D-Algorithm

Author(s): Jain, S.K. ; Agrawal, V.D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1983
Conference Location: Miami Beach, FL, USA, USA
Conference Date: 27 June 1983
Page(s): 64 - 70
ISBN (Paper): 0-8186-0026-8
ISSN (Paper): 0738-100X
DOI: 10.1109/DAC.1983.1585627
Regular:

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses.... View More

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