1196-1987 IEEE Standard for a Simple 32-Bit Backplane Bus: NuBus

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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1988
Status: inactive
Page Count: 140
ICS Code (Microprocessor systems): 35.160
ISBN (Online): 0-7381-2347-1
DOI: 10.1109/IEEESTD.1988.122651

Abstracts

Standard

The standard describes a computer backplane bus optimized for 32-bit transfers, multiprocessor operations, and simplicity. In brief, this is a synchronous (10 MHz). multiplexed, multimaster bus that provides a strictly fair arbitration mechanism. The only bus transfers are read and write (and block transfer versions of each of these) to a single 32-bit address space. Geographic slot addressing and nondaisy-chain arbitration scheme make system configuration simpler by eliminating switches and jumpers. This minimalist approach results in a conceptually straightforward bus with a small pin count (51 active signal lines).<>

Document History

1196-1987 - IEEE Standard for a Simple 32-Bit Backplane Bus: NuBus
January 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The standard describes a computer backplane bus optimized for 32-bit transfers, multiprocessor operations, and simplicity. In brief, this is a synchronous (10 MHz). multiplexed, multimaster bus that provides a strictly fair arbitration mechanism. The only bus transfers are read and write (and block ...

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