1296-1987 IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II

inactive - Reaffirmed , Withdrawn
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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 3 August 1988
Status: inactive
Page Count: 260
Page(s): 1 - 260
ICS Code (Interface and interconnection equipment): 35.200
ISBN (Online): 978-0-7381-3153-5
DOI: 10.1109/IEEESTD.1988.122654

Abstracts

Standard

The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high- performance backplane bus intended for use in multiple-microprocessor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state- of-the-art operation and to allow the implementation of cost-effective high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry is provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered. This document also contains IEEE Std 1101-1987, IEEE Standard for Mechanical Core Specifications for Microcomputers.

Document History

1296-1987 - IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II
August 3, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high- performance backplane bus intended for use in multiple-microprocessor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz ...

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