62530-2011 SystemVerilog Unified Hardware Design, Specification, and Verification Language

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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 19 May 2011
Status: active
Page(s): 1 - 1,294
ICS Code (Industrial automation systems): 25.040
ICS Code (Languages used in information technology): 35.060
ISBN (Online): 978-0-7381-6607-0
DOI: 10.1109/IEEESTD.2011.5944940

Abstracts

Standard

This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.

Document History

62530-2011 - SystemVerilog Unified Hardware Design, Specification, and Verification Language
May 19, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog s...

62530:2007 (E), IEEE Std 1800-2007 - IEC Standard for Systemverilog - Unified Hardware Design, Specification, and Verification Language (Adoption of IEEE Std 1800-2005)
January 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This standard provides a set of extensions to the IEEE 1364/sup TM/Verilog hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including cov...

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