1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 11 October 2004
Status: inactive
Page Count: 119
Page(s): 1 - 118
ICS Code (Languages used in information technology): 35.060
ISBN (Electronic): 978-0-7381-4065-0
DOI: 10.1109/IEEESTD.2004.94802

Abstracts

Standard

This document specifies a standard for use of very high-speed integrated circuit hardwaredescription language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructsare identified that should be ignored or flagged as errors.

Document History

1076.6-2004 - IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
October 11, 2004 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This document specifies a standard for use of very high-speed integrated circuit hardwaredescription language (VHDL) to model synthesizable register-transfer level digital logic. Astandard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset ofthe VHDL language, whi...

1076.6-1999 - IEEE Standard for VHDL Register Transfer Level Synthesis
March 10, 2000 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.

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