1005-1998 IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays

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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Status: inactive
Page Count: 129
ICS Code (Transistors): 31.080.30
ISBN (Paper): 0-7381-0620-8
ISBN (Online): 0-7381-3952-1
DOI: 10.1109/IEEESTD.1998.89425

Abstracts

Standard

Summary form only given. This standard describes the underlying physics and the operation of floating gate memory arrays, specifically, UV erasable EPROM, byte rewritable E/sup 2/PROMs, and block rewritable "flash" EEPROMs. In addition, reliability hazards are covered with focus on retention, endurance and disturb. There are also clauses on the issues of testing floating gate arrays and their hardness to ionizing radiation.

Document History

1005-1998 - IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays
January 1, 1998 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Summary form only given. This standard describes the underlying physics and the operation of floating gate memory arrays, specifically, UV erasable EPROM, byte rewritable E/sup 2/PROMs, and block rewritable "flash" EEPROMs. In addition, reliability hazards are covered with focus on retention, endura...

1005-1991 - IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays
October 17, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An introduction to the physics unique to this type of memory and an overview of typicalarray architectures are presented. The variations on the basic floating gate nonvolatile cellstructure that have been used in commercially available devices are described. The variousreliability considerations inv...

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