1181-1991 IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization

inactive
Buy Now
Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Status: inactive
Page Count: 36
ICS Code (Integrated circuits. Microelectronics): 31.200
ISBN (Online): 0-7381-2388-9
DOI: 10.1109/IEEESTD.1991.101074

Abstracts

Standard

Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integrated circuit process architecture so that different approaches can be scientifically compared. This allows the evaluation of the process capabilities on a 'worst-case' recommended structure and test method independent of actual integrated circuit product topographical latchup layout practices. Test structures and test philosophy are covered.<>

Document History

1181-1991 - IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
January 1, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integ...

Advertisement